1. Field of the Invention
This invention relates to a semiconductor device in which a multilayer interconnection layer to be electrically connected with a conductive layer via a contact hole has an improved structure, and also to a method of manufacturing such semiconductor device.
2. Description of the Related Art
In conventional semiconductor devices, as one of the simplest structures for wire portions leading from a conductive layer formed in the semiconductor substrate by diffusion of impurities, a structure in which a metal conductive layer such as aluminum, etc., is coated over the insulating layer after the insulating layer is provided with the contact hole is currently known.
In the manufacturing process for contact holes and leading wires such as of modern LSI, thanks to advances of photolithographic and etching technology, it is possible to form contact holes of about 1 .mu.m diameter in an insulating layer of about 1 .mu.m thickness; the inner wall of the contact hole is coated with a metal layer by sputtering. In this conventional method, however, since the contact hole has a very small open width of less than 1 .mu.m and has a steep side wall, the step and hence uneven portions of the contact hole cannot be covered by wiring metal with an adequate degree of step coverage, thus lowing the reliability of wiring.
In order to solve the problems, a concept of changing the deposition conditions for forming electrodes is disclosed in Japanese Patent Laid-Open Publication No. SHO 61-117829, a concept of forming a refractory metal coating by vapor is disclosed in Japanese Patent Laid-Open Publications Nos. SHO 59-61146 and 59-61147, and a concept of filling up the contact hole with refractory metal is disclosed in Japanese Patent Laid-Open Publications Nos. SHO 60-130825, 60-176230 and 61-97825.
In any of the foregoing prior art technologies, after contact holes have been formed in an insulating layer lying over the conductive layer in the form of an impurity diffusion layer formed on a semiconductor substrate, a metal coating is provided thereover. Therefore, the conductive layer having the semiconductor nature and the wiring metal are in direct contact with each other. As a result, even though the reliability of wiring could be improved by filling up the contact hole with the refractory metal having a high conductivity, the contact resistance between the wiring metal material and the semiconductor conductive layer would increase along with the downsizing of contact hole. This is true because of a resistance and a Shottky barrier in the contact portion between the semiconductor and metal due to the difference in energy level, so that the increase of resistance would become more remarkable as the semiconductor-metal contact area become smaller. Because the impurity diffusion layer must be made thinner along with the downsizing of the semiconductor device, it is necessary to reduce the impurity concentration of the impurity diffusion layer and also to lower the temperature for heat treatment. It is therefore difficult to reduce the contact resistance between the semiconductor conductive layer and wiring metal at the contact hole portion.
According to the prior art technology, since the contact resistance between the metal wiring layer of the contact hole portion and the conductive layer of the semiconductor substrate, or the foundation wiring layer chiefly of silicon, would increase sharply as the size of the contact hole is to be very small, the working ability of the semiconductor device would be impaired, fixing a limit on the improvement of performance of the semiconductor device. Yet, if the diameter of the contact hole is large, as compared to the design rule for the remaining portions, in an effort to increase the contact resistance of the contact hole portion using the conventional technology, it goes against downsizing the semiconductor device.
For example, according to the technology disclosed in Japanese Patent Laid-Open Publication No. SHO 60-130825, adequate step coverage is secured by providing the side wall of the contact hole with a slant by isotropic etching using a hydrofluoric acid solution or the like while etching the insulating layer. However, by isotropic etching, the diameter of the upper part of the contact hole would increase so that downsizing of the semiconductor device is difficult to achieve.